(1) Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing the semiconductor devices, and in particular, to a semiconductor device which includes external connection pads and test pads.
(2) Description of the Related Art
With advancement in integration and functions of semiconductor devices (semiconductor integrated circuits), power consumption of semiconductor devices are increasing. At the same time, with the miniaturization of the processes, wire resistance and wire length are also increasing. In regards to this, in the structure where electrode pads are arranged on the periphery of a chip, a problem exists where securing stable power supply and stable circuit operation is difficult. In particular, at the time of screening in a wafer state with use of probe needles, resistance of the probes is further added, making the problem more noticeable.
There is a technique, for example, disclosed in Japanese Patent Application Publication No. 8-227921 (hereinafter, referred to as Patent Document 1) which addresses the problem that occurs at the time of screening in a wafer state with the structure where electrode pads for assembly and packaging are arranged on the periphery of the chip.
However, with further advancement in the integration and functions, there is a demand for securing stable power supply and stable circuit operation even after the assembly. In order to meet such demand, there is a proposed method which takes measures in the assembly and packaging. More specifically, the wire length within a chip is reduced by arranging area pads across the entire chip surface. This reduces the voltage decrease of power supply.
However, in the case of surface mount, there is a concern in reliability of assembly of bump connection portions. In order to address the concern, there is a technique where a pad region is separated, which is, for example, disclosed in Japanese Patent Application Publication No. 2002-90422 (hereinafter, referred to as Patent Document 2). Furthermore, for example, Japanese Patent Application Publication No. 2004-207501 (hereinafter, referred to as Patent Document 3) discloses a structure of an LSI chip where probing test pads are arranged on the periphery of the chip and surface mount pads are arranged in an area array in the region other than the periphery.